Juniper’s Aurrion Buyout: Tech Nightmare?

August, 2016

Juniper Networks probably had very good reasons for becoming more vertically integrated in the optical space including perhaps the need to internally control its supply of transceivers as well as maybe strengthen its competitive position by acquiring intellectual property. Yet, its purchase of Aurrion and its complex set of moving parts at what seems to be a rather handsome price for the componentry company’s investors appears even more questionable than the router firm's previous pickup of BTI Systems. Aurrion’s focus is on wafer integration, the same type of technology that Intel has struggled to commercialize in the past.

Although once again, following the industry in moving away from the original vision of silicon photonics, in our opinion, this particular adoption of a hybrid platform is truly challenging in placing tiny layers of Indium Phosphide onto the Si wafer. Putting aside the apparent difficulties involved with the lack of CMOS-compatible tools and processes, the aligning and packaging of the two components together seems too expensive, and does not make sense to us.

In order to produce high-end gear, achieving the optimal performance out of all of the components is a necessity. With integration, there are tradeoffs and so one cannot get the best results. For example, the final shakeout in the market may turn out to be using InP for dumb light sources as well as detectors, while employing silicon for everything else.

In addition, silicon devices are only inexpensive with very high volumes – millions of units. Mask costs, big wafer lots, etc. are not really compatible in our optical industry, which tends to put out only tens of thousands of parts per quarter.

Regarding Juniper’s spending on optical components, it has been on the rise. In contrast, we understand that Cisco Systems’ expenditures of this type have generally been flat.

Evidently, with price erosion occurring so quickly, Cisco is positioned internally (including with its in-house transceivers) to not have to raise its spending to produce more widgets. So, as the volume of optical elements significantly increased at Juniper, it apparently decided to try to catch up to its archrival concerning lowering its development cost with its latest buyout.

We are also wondering whether Juniper took a hard look at possibly acquiring Skorpios Technologies. Certainly, in terms of proximity of the operations, Aurrion would have had a decisive edge.

Moreover, although Skorpios has somewhat similar core technology to Aurrion, we would say that the approach of the former is even more daunting to pull off. Obtensively, Skorpios digs fairly deep holes into the silicon and places relatively big chunks of InP. So, instead of just a little bit of light needed to leak into the InP resulting in optical gain (in the case of Aurrion’s solution), the light has to transition fully from the Si into the InP with the Skorpios design.

[written by Mark Lutkowitz]

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Andy Sun
August, 2016
It's all about the volume or wafer starts to be exact. I've been showing this simple math to others: with a typical die size of Si photonics transceiver chip, a 300mm wafer will produce ~1000 dies. The total addressable datacom market for Si photonics to take on III-V (non-VCSEL, multi-channel that I guess we both agree on) requires no more than 1000 wafers per year. It's ~0.5% shipment of ST's Crolles fab where Luxtera's chips are made. And yeah, it can not be combined with other IC or MEMS processes that the same fab produces regularly. I think making it with 65nm node is a very risky decision that Luxtera made. With the volume and with the huge development cost (that Luxtera may fail to completely fulfill) for this non-standard process, the outcome is that ST decided to compete with its customer and stop offering the very process to general public. It is after all a meaningful (though not very much) revenue for ST, IF it sells as a complete chipset instead of being a foundry. My opinion is that if one want to leverage the mature Si ecosystem (as everyone claims), he/she needs to respect the economic model of this ecosystem that volume (wafer starts) drives what you can do with the ecosystem not the other way around. But the interesting thing now is that a lot money (from both VC and government) has been poured into developing the processes in a number of fabs, some with piled-up fabricated well-performed chips have to sell no matter if it justifies the development cost. It could further complicate the already thin-margin industry.
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Mark Lutkowitz
August, 2016
Yes, I believe we are agreeing regarding the future of silicon photonics. You imply one of the conditions for it to be accepted is the availability of silicon merchant foundries. When or what event would need to happen for silicon foundry services to be offered to the general public?
Andy Sun
August, 2016
I generally agree with your assessment on Si Photonics although my success would depend on the recognition of it by the industry:) I've been long thinking that Si Photonics start-ups tend to over-invested in the technology considering the market size. And there is still this foundry problem that gives headaches to all Si Photonics companies (especially smaller ones). It took Aurrion a long time to secure a reliable foundry partner who accepts III-V materials on Si wafers (even if they form a III-V Si hybrid wafer for foundry to start with), especially for a moderate, if not small, wafer starts. This acquisition implies that they have demonstrated a solid partnership with its foundry, which, I believe just like the Luxtera-ST one, is still an exclusive partnership instead of a fabless-foundry model.

Intel collaborated with Prof. John Bowers (Aurrion's founder and chairman) since the beginning and later developed some know-how internally for their own demoed prototypes. Intel has the obvious advantage that there may be a number of small half-empty fabs at its disposal to do such non-traditional processes. Intel seems determined to make some moves this year. I did see surprising changes in its strategy after Alexis took place of Mario to direct the Si Photonics Group (now part of the Connectivity Group).

p.s. Intel/Aurrion's approach does not require precise alignment between III-V dies and Si wafers prior to bonding which is the key advantage they promoted. The difficult is about the bonding yield (thousands individual dies bonding on a wafer sequentially followed by complex thin-down processes) and the acceptance of Si foundries. And you're quite right on the compromise on the performance which involves fundamental issues in addition to engineering ones.